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sy56040ar low voltage 1.2v/1.8v/2.5v cml 4x4 crosspoint switch 6.4gbps, 5ghz precision edge is a registered trademark of micrel, inc. mlf and micro leadframe are registered trademarks of amkor technology. micrel inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax + 1 (408) 474-1000 http://www.micre l.com september 2008 m9999-093008-a hbwhelp@micrel.com or (408) 955-1690 general description the sy56040ar is a fully differential, low voltage 1.2v/1.8v/2.5v cml 4x4 crosspoint switch. the sy56040ar can process clock signals as fast as 5ghz or data patterns up to 6.4gbps. the differential input includes micrels unique, 3-pin input termination architecture that interfaces to lvpecl, lvds or cml differential signals as small as 100mv (200mv pp ) without any level-shifting or termination resistor networks in the signal path. for ac-coupled input interface applications, an internal voltage reference is provided to bias the v t pin. the outputs are 400mv cml, with extremely fast rise/fall times guaranteed to be less than 80ps. the sy56040ar operates from a 2.5v 5% core supply and a 1.2v/1.8v/2.5v 5% output supply and is guaranteed over the full industrial temperature range (C 40c to +85c). the sy56040ar is part of micrels high-speed, precision edge ? product line. datasheets and support documentation can be found on micrels web site at: www.micrel.com . precision edge ? features ? 1.2v/1.8v/2.5v cml 4x4 crosspoint switch ? guaranteed ac performance over temperature and voltage: C dc to 6.4gbps throughput C <400ps typical propagation delay (in-to-q) C <25ps typical output skew C <80ps rise/fall times ? ultra-low jitter design C <1ps rms cycle-to-cycle jitter C <10ps pp total jitter C <1ps rms random jitter C <10ps pp deterministic jitter ? high-speed cml outputs ? 2.5v 5% , 1.2v/1.8v/2.5v 5% power supply operation ? industrial temperature range: C40c to +85c ? available in 44-pin (7mm x 7mm) mlf ? package applications ? data distribution: oc-48, oc-48+fec ? sonet clock and data distribution ? fibre channel clock and data distribution ? gigabit ethernet clock and data distribution markets ? storage ? ate ? test and measurement ? enterprise networking equipment ? high-end servers ? access ? metro area network equipment downloaded from: http:///
micrel, inc. sy56040ar september 2008 2 m9999-093008-a hbwhelp@micrel.com or (408) 955-1690 functional block diagram truth table input select address table sin1 sin0 input 0 0 in0 0 1 in1 1 0 in2 1 1 in3 output select address table sout1 sout0 output 0 0 q0 0 1 q1 1 0 q2 1 1 q3 downloaded from: http:///
micrel, inc. sy56040ar september 2008 3 m9999-093008-a hbwhelp@micrel.com or (408) 955-1690 ordering information (1) part number package type operating range package marking lead finish SY56040ARMY mlf-44 industrial SY56040ARMY with pb-free bar-line indicator matte-sn SY56040ARMYtr (2) mlf-44 industrial SY56040ARMY with pb-free bar-line indicator matte-sn notes: 1. contact factory for die availability. dice are guaranteed at t a = 25c, dc electricals only 2. tape and reel. pin configuration 44-pin mlf ? (mlf-44) downloaded from: http:///
micrel, inc. sy56040ar september 2008 4 m9999-093008-a hbwhelp@micrel.com or (408) 955-1690 pin description pin number pin name pin function 17,15 10,8 4,2 41,39 in0, /in0 in1,/in1 in2,/in in3,/in3 differential inputs: these input pairs are the differential signal inputs to the device. they accept differential signals as small as 100mv (200mv pp ). each input pin internally terminates with 50 ? to the vt pin. note that these inputs will default to an indeterminate state if left open. please refer to the interface applications section for more details. 16 9 3 40 vt0 vt1 vt2 vt3 input termination center-tap: each side of the differential input pair terminates to a vt pin. this pin provides a center-tap to a termination network for maximum interface flexibility. an internal high impedance resistor divider biases vt to allow input ac-coupling. for ac-coupling, bypass vt with a 0.1f low esr capacitor to vcc. see interface applications subsection and figure 2a. 18 19 sin0 sin1 these single-ended ttl/cmos-compatible inputs address the data inputs during switch configuration. note that this input is internally connected to a 25k ohm pull- up resistor and will default to a logic high state if left open. 38 37 sout0 sout1 these single-ended ttl/cmos-compatible inputs address the data outputs during switch configuration. note that these inputs are internally connected to a 25k ? pull- up resistor and will default to logic high state if left open. 5 7 config load these single-ended ttl/cmos-compatible inputs control the transfer of the addresses defined by sin0/1 and sout0/1. see switch configuration, address table and timing diagram sections for more details. note that these inputs are internally connected to a 25k ? pull-up resistor and will default to logic high state if left open. 1. load: loads configurations into first set of latches. after programming sin and sout with input and output address respectively, pulse the load signal with a low to high to low signal to latch sin and sout. four load pulses are needed, each load pulse for each output. see simplified control circuit and switch configuration description on page 9 for further clarification. 2. config: loads new configuration into the second set of latches and updates switch configuration. after loading, pulse config with a low to high to low signal to load/transfer the latched signal to the output. see simplified control circuit and switch configuration description on page 9 for further clarification. if the load and config control signals are floating, one of the output pairs is set by the programmed sin and sout addresses, as shown in address tables. for the remaining outputs, setup is random at power up or from previous programmed states. 23,24 26,27 29,30 32,33 q0, /q0 q1, /q1 q2, /q2 q3, /q3 cml differential output pairs: differential buffered copy of the selected input signal. the output swing is typically 390mv. see interface application subsection for termination information. 6 vcc positive power supply: bypass with 0.1uf//0.01uf low esr capacitors as close to the v cc pin as possible. supplies input and core circuitry. 22,25,28,31,34 vcco output supply: bypass with 0.1uf//0.01uf low esr capacitors as close to the v cco pins as possible. supplies the output buffer. 12,13,20,21,35, 36,43,44 gnd, exposed pad ground: exposed pad must be connected to a ground plane that is at the same potential as the ground pin. 1,11,14,42 nc not connected. downloaded from: http:///
micrel, inc. sy56040ar september 2008 5 m9999-093008-a hbwhelp@micrel.com or (408) 955-1690 absolute maximum ratings (1) supply voltage (v cc ) ............................... C0.5v to +3.0v supply voltage (v cco ) ............................. C0.5v to +2.7v v cc - v cco .........................................................<1.8v v cco - v cc .........................................................<0.5v input voltage (v in ) ............................C0.5v to v cc + 0.5v cml output voltage (v out ) ................0.6v to v cco +0.5v current (v t ) source or sink current on vt pin .................100ma input current operating ratings (2) supply voltage (v cc ) ......................... 2.375v to 2.625v (v cco ).............................................. 1.14v to 2.625v ambient temperature (t a ).................... C40c to +85c package thermal resistance (3) mlf ? still-air ( ja ) ............................................40c/w junction-to-board ( jb ) .........................20c/w source or sink current on (in, /in) .................50ma maximum operating junction temperature.......... 125c lead temperature (soldering, 20sec.) .................. 260c storage temperature (t s ) ....................C65c to +150c dc electrical characteristics (4) t a = C40c to +85c, unless otherwise stated. symbol parameter condition min typ max units v cc power supply voltage range v cc v cco v cco v cco 2.375 1.14 1.7 2.375 2.5 1.2 1.8 2.5 2.625 1.26 1.9 2.625 v v v v i cc power supply current max. v cc 155 200 ma i cco power supply current no load. max. v cco 64 84 ma r in input resistance (in-to-v t , /in-to-v t ) 45 50 55 ? r diff_in differential input resistance (in-to-/in) 90 100 110 ? v ih input high voltage (in, /in) in, /in 1.2 v cc v v il input low voltage (in, /in) v il with v ihmin = 1.2v 0.2 v ih C0.1 v v ih input high voltage (in, /in) in, /in 1.14 v cc v v il input low voltage (in, /in) v il with v ihmin = 1.14v (1.2v-5%) 0.66 v ih C0.1 v v in input voltage swing (in, /in) see figure 3a 0.1 1.0 v v diff_in differential input voltage swing (|in - /in|) see figure 3b 0.2 2.0 v v t_in voltage from input to v t 1.28 v notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rat ing only and functional ope ration is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to abs olute maximum ra tings conditions for extended periods may affect device reliability. 2. the data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potent ial on the pc b. jb and ja values are determined for a 4-layer board in still-air number, unless otherwise stated. 4. the circuit is designed to meet the dc specifications shown in the above table afte r thermal equilibrium has been establishe d. downloaded from: http:///
micrel, inc. sy56040ar september 2008 6 m9999-093008-a hbwhelp@micrel.com or (408) 955-1690 cml outputs dc electrical characteristics (5) v cco = 1.14v to 1.26v, r l = 50 ? to v cco, v cco = 1.7v to 1.9v; 2.375v to 2.625v, r l = 50 ? to v cco or 100 ? across the outputs. v cc = 2.375v to 2.625v. t a = C40c to +85c, unless otherwise stated. symbol parameter condition min typ max units v oh output high voltage r l = 50 ? to v cco v cco -0.020 v cco -0.010 v cco v v out output voltage swing see figure 3a 300 390 475 mv v diff_out differential output voltage swing see figure 3b 600 780 950 mv r out output source impedance 45 50 55 ? lvttl/cmos dc electrical characteristics (5) v cc = 2.5v 5%. t a = C40c to +85c, unless otherwise stated. symbol parameter condition min typ max units v ih input high voltage 2.0 v cc v v il input low voltage 0.8 v i ih input high current - 125 30 a i il input low current -300 a note: 5. the circuit is designed to meet the dc specifications shown in the above table afte r thermal equilibrium has been establishe d. downloaded from: http:///
micrel, inc. sy56040ar september 2008 7 m9999-093008-a hbwhelp@micrel.com or (408) 955-1690 ac electrical characteristics (6) v cco = 1.14v to 1.26v, r l = 50 ? to v cco, v cco = 1.7v to 1.9v, 2.375v to 2.625v, r l = 50 ? to v cco or 100 ? across the outputs. v cc = 2.375v to 2.625v. t a = C40c to +85c, unless otherwise stated. symbol parameter condition min typ max units nrz data 6.4 gbps f max maximum data rate/ frequency v out > 200mv clock 5 ghz 200 290 400 ps t pd propagation delay in-to-q config-to-q load/config-q 450 850 ps t pw pulse width of load/configig signal 1500 ps t s set-up time sin-to-load sin-to-load/config sout-to-load sout-to-load/config load-to-config config-to-load note 7, fig. 1b, fig. 1c 600 600 800 800 1400 300 ps t h hold time load-to-sin load/config-to-sin load-to-sout load/config-to-sout note 8, fig. 1b, fig. 1c 800 500 600 500 ps input-to-input skew note 9 25 50 ps output-to-output skew note 10 12 25 ps t skew part-to-part skew note 11 75 ps data random jitter note 12 1 ps rms deterministic jitter note 13 10 ps pp clock cycle-to-cycle jitter note 14 1 ps rms total jitter note 15 10 ps pp t jitter crosstalk induced jitter (adjacent channel) note 16 0.7 ps pp t r , t f output rise/fall times (20% to 80%) at full output swing. 20 50 80 ps differential i/o 4ghz 47 53 % duty cycle differential i/o 5ghz 45 55 % notes: 6. high frequency ac electrical values are guaranteed by design and characterization. 7. set-up time is the time a signal has to be present before the rising edge of the clock /control signal comes by. for example , t s (sin-load/config), requires the time sin has to transition before the l-h edge of the load/config signal asser ts. 8. hold time is the time a signal has to be present after the falling edge of the clock edge/cont rol signal comes by. for examp le, t h (load/config-sin) defines the time sin signal has to transition after the h-l edge of the load/config signal asserts. 9. input-to-input skew is the difference in time between 4 inputs, measured at the same output, for the same temperature, vol tage, and transition. 10. output-to-output skew is the difference in time between 4 outputs, receiving data from the same input, for the same tempera ture, voltage and transition. 11. part-to-part skew is defined for two parts with identical power supply voltages at the sa me temperature and no skew at the edges at the respective inputs. 12. random jitter is measured with a k28.7 pattern, measured at f max . 13. deterministic jitter is measured at 2.5gbps with both k28.5 and 2 23 C1 prbs pattern. 14. cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sampl e of adjacent cycle pairs . t jitter _ cc = t n Ct n+1 , where t is the time between rising edges of the output signal. 15. total jitter definition: with an ideal clock input frequency of f max (device), no more than one output edge in 10 12 output edges will deviate by more than the specified peak-to-peak jitter value. 16. crosstalk induced jitter is defined as the added jitter that results from signals applied to t he adjacent channel. it is m easured at the output. while applying a similar, differential clock frequency to both inputs that is asynchronous with resp ect to each other. downloaded from: http:///
micrel, inc. sy56040ar september 2008 8 m9999-093008-a hbwhelp@micrel.com or (408) 955-1690 switch configuration as shown in the simplified control circuit below, figure 1a, each output channel consists of two sets of latches. the first set of latches stores the sin information for each sout selected. the second set of latches transfers this stored information to the output mux circuitry. these latches are transparent when en is high and latched when en is low. two pins, load and config, control the programming. load is anded with the sout pins to route the sin data to the appropriate first set of latches. config subsequently transfers the information in the first set of latches to the second set of latches, which is connected to the output mux circuitry. there are two ways to program this device. the first is a dual control mode, as shown in figure 1b. first, all the input-output (sin-sout) information is loaded. second, this information is transferred to the output control circuitry. each load pulse loads the input information (sin) to be assigned to the output (sout). in maximum, four load pulses are applied, one load pulse for each output. note that load pulses are necessary only for undefined and/or modified input-output combinations. after all the input-output information is loaded, the config is pulsed to transfer and latch this information to the output control circuitry. the second programming method is the single control mode, shown in figure 1c, in which load and config are tied together. each individual output receives the appropriate input information in a one- shot control pulse. when one output is being programmed, the other outputs remain unaffected until its turn occurs. interface applications for input interface applications, see figures 4a through 4f. for cml output termination, see figures 5a through figure 5d. cml output termination with vcco 1.2v for vcco of 1.2v, figure 5a, terminate the output with 50 ? to1.2v, dc-coupled, not 100 ? differentially across the outputs. if ac-coupling is used, figure 5d, terminate into 50 ? - to-1.2v before the coupling capacitor and then connect to a high value resistor to a reference voltage. do not ac-couple with internally terminated receiver, such as 50 ? any-in input. ac-coupling will offset the output voltage by 200mv and this offset voltage will be too low for proper driver operation. any unused output pair needs to be terminated when vcco is 1.2v, do not leave floating. cml output termination with vcco 1.8v, 2.5v for vcco of 1.8v and 2.5v, refer to figure 5a and figure 5b, terminate with either 50 ? to vcco or 100 ? differentially across the outputs. see figure 5c for ac-coupling. input ac-coupling the sy56040ar input can accept ac-coupling from any driver. bypass vt with a 0.1f low esr capacitor to vcc as shown in figures 4c and 4d. vt has an internal high impedance resistor divider as shown in figure 2a, to provide a bias voltage for ac-coupling. figure 1a. simplified control circuit downloaded from: http:///
micrel, inc. sy56040ar september 2008 9 m9999-093008-a hbwhelp@micrel.com or (408) 955-1690 timing diagrams figure 1b. dual-control mode timing diagram figure 1c. single-control mode timing diagram note 17. invalid and valid refer to configurations being changed. all outputs with unchanged configurations remain valid. downloaded from: http:///
micrel, inc. sy56040ar september 2008 10 m9999-093008-a hbwhelp@micrel.com or (408) 955-1690 typical characteristics v cc = 2.5v, v cco =1.2v, gnd = 0v, v in = 100mv, r l = 50 ? to 1.2v, t a = 25c, unless otherwise stated. functional characteristics v cc = 2.5v, v cco = 2.5v, gnd = 0v, v in = 100mv, r l = 50 ? to 2.5v, data pattern: 2 23 -1, t a = 25c, unless otherwise stated. downloaded from: http:///
micrel, inc. sy56040ar september 2008 11 m9999-093008-a hbwhelp@micrel.com or (408) 955-1690 input and output stage figure 2a. simplified differential input buffer figure 2b. simplified cml output buffer single-ended and differential swings figure 3a. single-ended swing figure 3b. differential swing downloaded from: http:///
micrel, inc. sy56040ar september 2008 12 m9999-093008-a hbwhelp@micrel.com or (408) 955-1690 input interface applications figure 4a. cml interface (dc-coupled, 1.8v, 2.5v) option: may connect v t to v cc figure 4b. cml interface (dc-coupled, 1.2v) figure 4c. cml interface (ac-coupled) figure 4d. lvpecl interface (ac-coupled) figure 4e. lvpecl interface (dc-coupled) figure 4f. lvds interface downloaded from: http:///
micrel, inc. sy56040ar september 2008 13 m9999-093008-a hbwhelp@micrel.com or (408) 955-1690 cml output termination figure 5a. 1.2v, 1.8v or 2.5v cml dc-coupled termination figure 5b. 1.8v or 2.5v cml dc-coupled termination figure 5c. cml ac-coupled termination (v cco 1.8v or 2.5v) figure 5d. cml ac-coupled termination (v cco 1.2v only) related product and support documents part number function datasheet link hbw solutions new products and termination application notes http://www.micrel.com/page.do?page=/product- info/as/hbwsolutions.shtml sy58040u 4x4 cml switch with internal i/o term. http://www.micrel.com/_pdf/hbw/sy58040u.pdf#page=3 sy89540u 4x4 lvds switch with internal i/o term. http://www.micrel.com/_pdf/hbw/sy89540u.pdf#page=3 downloaded from: http:///
micrel, inc. sy56040ar september 2008 14 m9999-093008-a hbwhelp@micrel.com or (408) 955-1690 package information 44-pin micro leadframe ? (mlf-44) micrel, inc. 2180 fortune drive san jose, ca 95131 us a tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http://www.micrel.com the information furnished by micrel in this data sheet is believed to be accurate and reliable. how ever, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time wi thout notification to the customer. micrel products are not designed or authorized for use as components in life support appliances, devices or s ystems where malfu nction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or system s that (a ) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonabl y expected to resul t in a significant injury to the user. a purchasers use or sale of micrel products for use in lif e support appliances, devices or systems is a purchasers own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sa le. ? 2008 micrel, incorporated. downloaded from: http:///

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